The documents distributed by this server have been provided by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, not withstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder.

Host Bypassing: Direct Data Piping from the Network to the Hardware Accelerator

Key:KEM+21
Author:Ralf Kundel, Kadir Eryigit, Jonas Markussen, Carsten Griwodz, Osama Abboud, Rhaban Hark, Ralf Steinmetz
Date:December 2021
Kind:In proceedings - use for conference & workshop papers
Publisher:IEEE
Book title:14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip
Abstract:Computer networks have become very important and influential over the last years for many common services such as Internet connectivity as well as time-sensitive applications such as videotelephony. Furthermore, approaches like in-network computing enable the offloading of latency-critical and highperformance network functions into the network, e.g. 5G network functions, to enable such time-sensitive applications. In this work, we show how FPGAs in PCIe-based systems, which are typically used as hardware accelerators for latencycritical in-network functions, can be integrated into the data path. Our approach, named host bypassing, allows direct data transfer from the network interface to the accelerator and accomplishes substantial performance benefits over existing state-of-the-art approaches. Our detailed evaluation results demonstrate the possibility of achieving deterministic low latency while operating under heavy load without any packet loss. In addition, fewer CPU resources are required.
Full paper (pdf)

[Export this entry to BibTeX]

[back]